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hi-sincerity microelectronics corp . spec. no. : i c 200912 i ssued date : 2009. 07. 15 revised date : page no. : 1/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification h6850 series novel low cost green-power pwm controller with low emi technique feature z low cost, pwm&pfm&crm (cycle reset mode) z low start-up current (about 3 a) z low operating current (about 1.2ma) z current mode operation z under voltage lockout (uvlo) z built-in synchronized slope compensation z built-in low emi technique z programmable pwm frequency z audio noise free operation z leading edge blanking on sense input z constant output power limiting for universal ac input range z sot-23-6 l sop8 and dip-8 pb-fr ee packaging z good protection coverage with auto self-recovery z compatible with sg6848 (6849) / sg5701/sg5848/ld7535 (7550) / ob2262 (2263)/ob2278 2279 z complete protection with ? soft clamped gate output voltage 18.0v ? vdd over voltage protect 34.0v ? cycle-by-cycle current limiting ? output scp (short circuit protection) ? output olp (over load protection) ? high-voltage cmos process with esd applications z switching ac/dc adaptor z battery charger z open frame switching power supply z standby power supplies z set-top box power supplies z 384x replacement general description the h68 50 is a highly integrated low cost current mod e pwm controller , which i s ideal for small power cur r en t mode of of fline ac-dc fly- back converter applic ations. making use of external resistors, the ic changes the operating frequency and automatically enters the pfm/crm ( c ycle reset mode) und er light-load/zer o -loa d conditions. this can minimize st andb y powe r consumption an d achieve powe r- saving functions. with a very lo w st art-up current, the h685 0 could use a large value st art-up resistor (2m ? ). built-in synchronized slo pe compens ation enhances the st ability of the syste m and avoids sub-harmonic oscillation. d y namic peak current limiting circuit minimize s output powe r chang e caused by delay time of the system over a universal ac input range. leading edge blanking circuit on current sense input could remo ve the signal glitch due to snubber circuit diode reverse recovery and thus greatly reduces the external component count and system cost in the design. cycle-by-cycle current limiting ensures safe operation even during short-circuit. excellent emi performance is achieved built-in soft driver and low emi technique. the h68 5 0 offers perfect protection like ovp(over voltage prote c tion) olp(over load protection) scp(short circuit protection) otp sense fault protection and ocp(over current protection). the h6850?s output driver is soft clamped to maximum 18.0v to protect the power mosfet. h6850 is offered in sot-23-6l, sot-8 and dip-8 packages. http://
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 2/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification pin assignment part number description h6850nf sot26, pb-fr ee,in t/r H6850S sop-8, p b-free in t/r h6850p dip-8, pb-fre e in tube pin descriptions package function description sot-26 dip-8 pin6: gate pin1: gate totem-pole output to drive the external power mosfet pin5: vdd pin2: vdd supply voltage pin. pin3: nc nc pin. pin4: sense pin4: sense current se ns e p i n, a r e s i st or co nne c t s t o se nse t h e mosfet current. pin3: ri pin5: ri this p i n is t o pr o g ram the sw it c h i n g freque ncy . by connect in g a resisto r to g r ou nd to set th e switching frequency. pin6: nc nc pin pin2: fb pin7:fb voltage feedback pin. output current of this pin could controls the pwm duty cycle olp and scp. 3 1 2 4 6 5 sot-26 12 3 4 5 6 7 8 dip -8(sop-8) pin1: gnd pin8: gnd gnd pin typical application h6850
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 3/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification block diagram simplified internal circuit architecture absolute maximum ratings symbol parameter rating unit v dd supply voltage pin voltage 40 v i ovp vdd ovp maximal enter current 20 ma v fb input voltage to fb pin -0.3 to 6v v v sen input voltage to sen pin -0.3 to 6v v p d power dissipation 300 mw esd capability, hbm model 2500 v esd capability, machine model 250 v sot-23-6l (20s) 220 dip-8 (10s) 260 t l lead temperature (soldering) sop-8 (10s) 230 t stg storage temperature range -55 to + 150 recommended operation condition symbol parameter min ~ max unit vdd vdd supply voltage 10~30 v ri ri pin resistor value 100 k ohm t oa operation ambient temperature -20~85 p omax maximal output power 0~80 w f pwm frequency of pwm 30~150 khz
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 4/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification electrical characteristics ( ta=25c unless otherwise noted, v dd = 16v ) symbol parameter conditions min. typ. max. unit supply voltage (v dd pin) i st startup current 3.0 20.0 a v fb =0v 3.0 ma v fb =3v 1.2 ma i ss operating current v fb =open 0.8 ma vdd on turn-on threshold voltage 13.0 14.0 15.0 v vdd off turn-off threshold voltage 7.8 8.8 9.8 v vdd clamp vdd clamp voltage i vdd =10ma 34.0 v vdd ais anti intermission surge vdd voltage 9.4 v voltage feedback (fb pin) i fb short circuit current v fb =0v 0.7 ma v fb open loop voltage v fb =open 4.8 v i fb_0d zero duty cycle fb current 0.59 ma i pfm enter pfm fb current 0.50 ma i crm enter crm fb current 0.55 ma v pfm enter pfm threshold v fb 1.80 v v crm enter crm threshold v fb 1.40 v i olp&scp enter olp&scp fb current 170 ua v olp&scp enter olp&scp fb voltage 3.7 v t olp&scp olp&scp min. delay time ri=100k 33 35 50 ms current sensing (sen pin) v th_l sen maximu m voltage le vel dmin=0% ri=1 00k, fb=3.3v 0.80 v v th_h sen maximu m voltage level(dmax=78%) ri=1 00k, fb=3.3v 1.05 v t pd delay to output fb=3.3v 75 ns
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 5/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification r cs input impedance 40 k ? t leb leading edge blanking time ( leb ) ri=100k 300 ns oscillator (ri pin) f osc normal frequency ri=100kohm 60 65 70 khz f pfm pfm frequency ri=100kohm 22 khz dc max_w maximum duty cycle pwm ri=100kohm 78 % dc max _ f maximum duty cycle pfm ri=100kohm 78 % f temp frequency temp. stability -30-100 5 % t blank leading-edge blanking time 300 ns f jitter frequency jitter ri=100kohm -4 4 % gate drive output (gate pin) v ol output low level v dd =16v, i o =20ma 0.8 v v oh output high level v dd =16v, i o =20ma 10 v t r1 rising time c l =500pf 123 ns t f1 falling time c l =500pf 71 ns t r2 rising time c l =1000pf 248 ns t f2 falling time c l =1000pf 116 ns t r3 rising time c l =1500pf 343 ns t f3 falling time c l =1500pf 153 ns t r4 rising time c l =2000pf 508 ns t f4 falling time c l =2000pf 209 ns vg clamp output clamp voltage vdd=20v 18.0 v low emi technique f emi low emi frequency ri=100kohm 65 khz ? f_osc frequency modulation range /base frequency ri=100kohm -3 3 %
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 6/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification operation description current mode ) ( ) ( 6500 khz k ri f osc = compar ed t o voltag e mode contr o l, current mode control has a current feedback loop. when the voltage of the sense resistor peak current of the pr imary winding reaches the internal setting value v th , the register resets and the power mosfet cuts off. so, to detect and modulat e the peak current cycle-by-cycle could c ontrol the output of the power supply. the current feedback has a good linear modulation rate and a fast input and output dynamic im pact, and avoid the pole that the output filt er inductance brings and the two-class system descends to the one-class. so it widens the frequency range and optimizes overload protection and short circuit protection. for example, a 100k ? resistor ri could generate a 20ua constant current and a 65khz pwm switching frequency. the suggested operating frequency range of h6850 is within 50khz to 150khz. green power operation the pow er dissip a tion of switching mode powe r supply is very import ant in zero load o r lig ht load co ndition. the majo r dissipation results from conduction loss switching loss and cons ume of the control circuit. however, all of them relates to the switching frequency. there are many difference topologies has been implemented in different chip. the basic operation theory of all these approaches intends to reduce the switching frequency under light-load or no-load condition. startup current and under voltage lockout the startup current of h 6850 is se t to be very l o w so that a large valu e startup resistor can be used to minimize the powe r loss. for ac to dc adaptor with universal input range design, a 2 m ? , 1/8 w startup resistor and a 10uf/25v vdd hold ca pacitor could be used . the h6850`s green power function adapts pwm pfm and crm combining modulation. when ri resistor is 100k , the pwm frequency is 65khz in medium or heavy load operation. through modifying the pulse width, the h6850 could control output voltage. the current of fb pin increases when the load is in light condition and the internal mode controller enters pfm&pwm when the feedback current is over 0.5ma. the operation frequency of oscillator is to descend gradually. when the feedback current is over 0.55ma, the frequency of oscillator is invariable, namely 22khz. the turn-on and turn-off threshold of the h6850 is designed to 14v/8.8v. during startup, the hold-up capacitor must be charge to 14.0v through the startup resistor. the hysteresis is implemented to prevent the shutdown from t he voltage dip during startup. internal bias and osc operation a resistor connected between ri pin and gnd pin sets the internal constant current source to charge or discharge the internal fixed capacitor. the charge time and discharge time determines the internal clock speed and the switching frequency. increasing the resistance will reduce the value of the input current and reduce the switching frequency. the relationship between ri and pwm switching frequency follows the below equation within the ri allowed range. h6850 gr ee n-po w e r f un ction
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 7/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification to decrease the st andby consumption of the power supply, chip-rail introduces the cycle reset mode technology (crm). if the feedback current is over 0.59ma, mode controller of the h6850 would reset internal register all the time and cut off the gate pin. while the output voltage is lower than the set value, the register would be set, the gate pin operate again. so the frequency of the internal osc is invariable, the register would reset some pulses so that the practical frequency is decreased at the gate pin. internal synchronized slop compensation although there are more advantages of the current mode control than conventional voltage mode control, there are still several drawbacks of peak-sens ing current-mode converter, especially the open loop instability when it ope rates in higher than 50% of the duty-cycle. to solve this problem, the h6850 is introduced an internal slope compensation adding voltage ramp to the current sense input voltage for pwm generation. it improves the close loop stability greatly at ccm, prevents the sub-harmonic oscillati on and thus reduces the output ripple voltage. duty duty duty v max slop = = 4389 . 0 33 . 0 slop compensation current sensing & dynamic peak limiting the current flowing by the power mosfet co mes into being a volt age v sense on the sense pin cycl e-by-cycle, which comp ares to the internal reference volt age, and control s the rever s e of the internal register , limit s the peak curre nt imax of the primary of the transformer . the transforme r ener gy is 2 2 1 max i l e = . so ad justing the r sense can set the maximal o u tput powe r of the pow er su pple. the curre nt flowing by th e powe r mosfet has a n extr a value ( d p in t l v i = ) due to the system delay time that is from de tecting the curre nt throug h the sense pin to powe r mosfet of f in the h6850 (among these, v in is the primary win d ing volt age of the transformer and l p is the primary wi nd induct ance). v in rang es from 85v ac to 264v ac . to guar antee th e output p o w e r is a const ant for unive rsal input ac vol t age, there is a dynamic pea k limit circ uit to compensate the system delay t that t he system delay brings on. 1. 10 duty cycle v s en se 0. 65 0. 70 0. 75 0. 80 0. 85 0. 90 0. 95 1. 00 1. 05 10% 2 0% 30% 40 % 50% 60 % 7 0% 80 % 9 0% 0% olp&scp to protect the circuit from being damaged under the over load or short circuit condition, a smart olp&scp function is implemented in the h6850. when short circuit or over load occurs in the output end, the feedback cycle would enhance the voltage of fb pin, while the voltage is over 3.7v or the current from fb is below 170ua, the internal detective circuit would send a signal to shut down the gate and pull down the vdd voltage, then the circuit is restart. to avoid the wrong operation when circuit
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 8/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification over voltage protection (ovp) starts, the delay time is set. when the ri resistance is 100kohm , the delay time t olp&scp is between 33m s and 50ms. the relationship between ri and t olp&scp follows the below equ atio n. there is a 34v over-voltage protection circuit in the h6850 to improve the credibility and extend the life of the chip. when the vdd voltage is over 34v, the gate pin is to shutdown immediately and the vdd voltage is to descend rapidly. ) ( 10 6 3 ) ( 10 6 2 3 & 3 ms ri t ms ri scp olp < < anti intermission surge gate driver & soft clamped when the p o wer suppli e s change the heavy loa d to light load i mmediately , there could be tow phen omena caused by s y stem delay. they are output voltage overshot and intermission surge. to avoid it, the anti intermission surge is built in the h6850. if it occurs, the fb current is to increase rapidly, the gate would be cut off for a while, vdd pin voltage descends gradually. when vdd reaches 9.4v, the gate pin would operate again, which the frequency is 22khz. the h685 0? output designs a totem pole to drive a periphery power mosfet. the dead time is introduced to minimize the transfixion current during the output operating. the novel soft clamp technology is introduced to protect the periphery power mosfet from breaking down and current saturation of the zener. low emi technique the frequen cy low emi technique is introduced in the h6850. as following figure, the internal oscillatio n frequency is modulated b y itself. a whole surg e cycle includes 128 pulses and the jittering r anges from -4% to +4%. thus, the function could minimize the electromagnetic interferer from the powe r supply modul e. leading-edge blanking (leb) each time the power mosfet is switched on, a turn-on spike will inevitably occur at the sense pin, which would disturb the internal signal from the sampling of the r sense . there is a 300ns leading edge blanking time built in to avoid the effect of the turn-on spike, and the power mosfet cannot be switched off during the moment. so that the conventional external rc filtering on sense input is no longer required. 60k 65k 70 k ti m e frequency(hz) h6850 frequency low emi
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 9/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification characterization plots vdd=16v,ri=100kohm,t a =25 condition applies if not otherwise noted.
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 10/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 1 1 /13 h6850p , H6850S, h 6850nf hsm c pr oduct specification package demensions dip-8l dimensions millimeters inches symbol min. typ. max. min. typ. max. a 5.334 0.210 a1 0.381 0.015 a2 3.175 3.302 3.429 0.125 0.130 0.135 b 1.524 0.060 b1 0.457 0.018 d 9.017 9.271 10.160 0.355 0.365 0.400 e 7.620 0.300 e1 6.223 6.350 6.477 0.245 0.250 0.255 e 2.540 0.100 l 2.921 3.302 3.810 0.115 0.130 0.150 eb 8.509 9.017 9.525 0.335 0.355 0.375 ? 0 ? 7 ? 15 ? 0 ? 7 ? 15 ?
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 12/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification sot-23-6l dimensions in millimeters dimensions in inches symbol min max min max a 0.700 1.000 0.028 0.039 a1 0.000 0.100 0.000 0.004 b 1.397 1.803 0.055 0.071 b 0.300 0.559 0.012 0.022 c 2.591 3.000 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024
hi-sincerity microelectronics corp . spec. no. : i c 200804 i ssued date : 2008. 09. 19 revised date : page no. : 13/13 h6850p , H6850S, h 6850nf hsm c pr oduct specification sop-8l dimensions disclai m ers millimeter inch symbol min. typ. max. min. typ. max. a 1.346 1.752 0.053 0.069 a1 0.101 0.254 0.004 0.010 b 0.406 0.016 c 0.203 0.008 d 4.648 4.978 0.183 0.196 e 3.810 3.987 0.150 0.157 e 1.016 1.270 1.524 0.040 0.050 0.060 f 0.381x45 0.015x45 h 5.791 6.197 0.228 0.244 l 0.406 1.270 0.016 0.050 ? 0 8 0 8

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